1. Technical Field
The present disclosure relates to a semiconductor package in which a semiconductor chip is embedded and a manufacturing method thereof.
2. Description of the Related Art
In the related art, a semiconductor package in which a semiconductor chip is embedded has been proposed. For example, the semiconductor package includes a first insulating layer which is formed to cover a circuit forming surface (a surface on which an electrode pad is provided) and a side surface of the semiconductor chip. Moreover, a first wiring layer which is electrically connected to the electrode pad of the semiconductor chip and other insulating layers or wiring layers which are formed on the first wiring layer are provided on the first insulating layer (see e.g., JP-A-2008-300854).
However, in the related-art the semiconductor package, the semiconductor chip is embedded in one side of the first insulating layer in a thickness direction, and a multilayer wiring structure including the insulating layer and the wiring layer is formed on the other side of the first insulating layer. As such, the semiconductor chip is not embedded in the other side. With this configuration, a warpage occurs in the related-art semiconductor package.
More specifically, when the semiconductor chip contains silicon as a main component, the thermal expansion coefficient is substantially 3.4 ppm/° C., and Young's modulus is substantially 200 GPa. On the other hand, the first insulating layer or other insulating layers contain epoxy resin as a main component, the thermal expansion coefficient is substantially 8 ppm/° C. to 150 ppm/° C., and Young's modulus is substantially 0.03 GPa to 13 GPa. In addition, when the first wiring layer or other wiring layers contain copper as a main component, the thermal expansion coefficient is substantially 17.2 ppm/° C., and Young's modulus is substantially 118 GPa.
Due to differences in the physical property values (thermal expansion coefficient or Young' modulus), the first insulating layer side (one side of the semiconductor package) in which the semiconductor chip is embedded is not easily deformed by thermal stress or the like, but the other side in which the semiconductor is not embedded is easily deformed by thermal stress or the like. As a result, for example, in the semiconductor package, there is a problem that a warpage occurs and the first insulating layer side, in which the semiconductor chip is embedded, tends to be deformed in a convex shape.